rumors of Clipper hardware problems

[""L. Detweiler"" <ld231782@longs.lance.colostate.edu>]

The following came from D. Farber who is closely associated with NSF
Internet commitees and has been following Clipper development, as
received from an anonymous informant. Items:

1. list of Clipper committee members
2. more NIST irregularities around DSS
3. Clipper: low yield, average failure in 40 hours, `substantial
redesign', delayed up to a year?

If anyone forwards this past cypherpunks (e.g. Usenet) take out my and
D. Farber names.

===cut=here==

From: farber@central.cis.upenn.edu (David Farber)
Subject: technical review of the Slipjack algorithm
Date: Tue, 29 Jun 1993 16:42:24 -0500

In case anyone hasn'y picked this up yet, this is the list of individuals
who are participating in the technical review of the Slipjack algorithm:

Dorothy Denning, Georgetown U.
Walt Tubman, IBM (retired)
Ernie Brickell, Sandia Labs
Steve Kent, BBN
Dave Mayer, AT&T

According to Lynn McNulty (NIST), the group met for a few days last week
with NIST and NSA representatives.  They are now in the process of
formulating more questions for a second meeting with the government team. 
No word yet on the form, content or schedule of the group's report.



From: farber@central.cis.upenn.edu (David Farber)
Subject: "Digital Signature Scandal" a bit more
Date: Tue, 29 Jun 1993 16:40:57 -0500

During a discussion in DC today the following arose.

The Federal register announcement was dated and signed on 2 June 1993 (and
published on 8 June). The NIST Advisory Board mandated by the congress was
meeting at NIST on 2-5 June. They were not told about the announcement even
though the matter was of direct interest and importance to their assigned
task. Why??? Did someone have something to hide? 

I hear tell also that the Clipper chip's first run of final silicon was not
a winner. Chips failed after 40 hours. I also heard a rumor that the redo
would [delay] things for up to a year (sounds like a long time). Any better
info out there?

Dave

"Informant" [forwarded by D. Farber]:

"My info is that there were three parallel tests; your number comes from
the first, though the others were little better.

Batch I         n=8     mtbf= 41.5 hrs.

Batch II        n=11 mtbf= 49.0 hrs.

Batch III
                n=20    mtbf= 32.0 hrs.

My NSA source said that he thought that the difficulty was related to
thermal issues and that if environmental issues were addressed or at least audit
ed to assure proper operating environment the numbers might have been better.

I have been unable to get any 'hard' info re what actually happened and what
kind of a post mortem is taking place."

2.  Re chip health.  I heard the same story plus yield was very low.
I also understand that there is substantial redesign going on because
the story about defaulting to an all-0 key if the LEB were corrupted
was apparently true.